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3D nanosystems enable embedded abundant-data computing: special session paper.

, , , , , , , and . CODES+ISSS, page 29:1-29:2. ACM, (2017)

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Evaluation of Low-Voltage SRAM for Error-Resilient Augmented Reality Applications., , , and . SiPS, page 1-3. IEEE, (2021)3D nanosystems enable embedded abundant-data computing: special session paper., , , , , , , and . CODES+ISSS, page 29:1-29:2. ACM, (2017)Monolithic 3D integration: a path from concept to reality., , , , , and . DATE, page 1197-1202. ACM, (2015)A QDI Interconnect for 3D Systems Using Industry Standard EDA and Cell Libraries., , , , and . ASYNC, page 58-59. IEEE, (2023)Nano-engineered architectures for ultra-low power wireless body sensor nodes., , , , , , and . CODES+ISSS, page 23:1-23:10. ACM, (2016)A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques., , , , , , , , , and 6 other author(s). ISSCC, page 226-228. IEEE, (2019)A Uniform Latency Model for DNN Accelerators with Diverse Architectures and Dataflows., , , , , and . DATE, page 220-225. IEEE, (2022)11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint., , , , , , , , , and 3 other author(s). ISSCC, page 210-212. IEEE, (2024)Co-Optimization of SRAM Circuits with Sequential Access Patterns in a 7nm SoC Achieving 58% Memory Energy Reduction for AR Applications., , , , , , , and . VLSI Technology and Circuits, page 216-217. IEEE, (2022)System-Level Design and Integration of a Prototype AR/VR Hardware Featuring a Custom Low-Power DNN Accelerator Chip in 7nm Technology for Codec Avatars., , , , , , , , , and 2 other author(s). CICC, page 1-8. IEEE, (2022)