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Disambiguation of "Repossi, Matteo"

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A Low-Noise Design Technique for High-Speed CMOS Optical Receivers.

, , , , , , and . IEEE J. Solid State Circuits, 49 (6): 1437-1447 (2014)

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Matteo Garavoglia

Matteo Rini

Marco Matteo

Matteo Bertini

Matteo Gabba

 

Other publications of authors with the same name

A 24GHz Sub-Harmonic Receiver Front-End with Integrated Multi-Phase LO Generation in 65nm CMOS., , , and . ISSCC, page 216-217. IEEE, (2008)A wideband mm-Wave CMOS receiver for Gb/s communications employing interstage coupled resonators., , , , , , , , and . ISSCC, page 220-221. IEEE, (2010)22.9 A 1310nm 3D-integrated silicon photonics Mach-Zehnder-based transmitter with 275mW multistage CMOS driver achieving 6dB extinction ratio at 25Gb/s., , , , , , and . ISSCC, page 1-3. IEEE, (2015)A 25Gb/s low noise 65nm CMOS receiver tailored to 100GBASE-LR4., , , , , , and . ESSCIRC, page 221-224. IEEE, (2012)A Low-Noise Design Technique for High-Speed CMOS Optical Receivers., , , , , , and . IEEE J. Solid State Circuits, 49 (6): 1437-1447 (2014)A 3.2-to-7.3GHz Quadrature Oscillator with Magnetic Tuning., , , and . ISSCC, page 92-589. IEEE, (2007)12.2 A 4-Channel 200Gb/s PAM-4 BiCMOS Transceiver with Silicon Photonics Front-Ends for Gigabit Ethernet Applications., , , , , , , , , and 10 other author(s). ISSCC, page 210-212. IEEE, (2020)A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication., , , , , , , , , and . IEEE J. Solid State Circuits, 44 (4): 1306-1315 (2009)A sliding IF receiver for mm-wave WLANs in 65nm CMOS., , , , , , and . CICC, page 669-672. IEEE, (2009)A 3D-integrated 25Gbps silicon photonics receiver in PIC25G and 65nm CMOS technologies., , , , , and . ESSCIRC, page 131-134. IEEE, (2014)