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Disambiguation of "Baldi, Daniele"

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A Low-Noise Design Technique for High-Speed CMOS Optical Receivers.

, , , , , , and . IEEE J. Solid State Circuits, 49 (6): 1437-1447 (2014)

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Stefan Baldi

Doris Baldinger

Marco Baldi

Guido Baldi

Alvars Baldinch

 

Other publications of authors with the same name

A 3D-integrated 25Gbps silicon photonics receiver in PIC25G and 65nm CMOS technologies., , , , , and . ESSCIRC, page 131-134. IEEE, (2014)A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication., , , , , , , , , and . IEEE J. Solid State Circuits, 44 (4): 1306-1315 (2009)A 5th order gm-C low-pass filter with ±3% cut-off frequency accuracy and 220MHz to 3.3GHz tuning-range in 28nm LP CMOS., , , , , and . ESSCIRC, page 351-354. IEEE, (2014)A 3GHz Fractional-N All-Digital PLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction., , , and . ISSCC, page 344-345. IEEE, (2008)23.4 A 56Gb/s 300mW silicon-photonics transmitter in 3D-integrated PIC25G and 55nm BiCMOS technologies., , , , , and . ISSCC, page 404-405. IEEE, (2016)A 25Gb/s 3D-integrated silicon photonics receiver in 65nm CMOS and PIC25G for 100GbE optical links., , , , , , and . ISCAS, page 2334-2337. IEEE, (2016)A 12Gb/s 39dB loss-recovery unclocked-DFE receiver with bi-dimensional equalization., , , , , , , , and . ISSCC, page 164-165. IEEE, (2010)22.9 A 1310nm 3D-integrated silicon photonics Mach-Zehnder-based transmitter with 275mW multistage CMOS driver achieving 6dB extinction ratio at 25Gb/s., , , , , , and . ISSCC, page 1-3. IEEE, (2015)A 25Gb/s low noise 65nm CMOS receiver tailored to 100GBASE-LR4., , , , , , and . ESSCIRC, page 221-224. IEEE, (2012)Insights Into Wideband Fractional ADPLLs: Modeling and Calibration of Nonlinearity Induced Fractional Spurs., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 57-I (9): 2259-2268 (2010)