Author of the publication

Contact and junction engineering in bulk FinFET technology for improved ESD/latch-up performance with design trade-offs and its implications on hot carrier reliability.

, , , and . IRPS, page 3. IEEE, (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A Dedicated TLP Set-Up to Investigate the ESD Robustness of RF Elements and Circuits., , , and . Microelectron. Reliab., 45 (9-11): 1421-1424 (2005)A 10GHz Broadband Amplifier with Bootstrapped 2kV ESD Protection., , , , , and . ISSCC, page 550-551. IEEE, (2007)Electronic design automation (EDA) solutions for ESD-robust design and verification., , , , and . CICC, page 1-8. IEEE, (2012)High-Voltage-Tolerant I/O Circuit Design for USB 2.0-Compliant Applications., , , and . CICC, page 491-494. IEEE, (2007)ESD protection for the deep sub micron regime - a challenge for design methodology.. VLSI Design, page 809-. IEEE Computer Society, (2004)Circuit design issues in multi-gate FET CMOS technologies., , , , , , , , , and 5 other author(s). ISSCC, page 1656-1665. IEEE, (2006)Physics of Current Filamentation in ggNMOS Revisited: Was Our Understanding Scientifically Complete?, , , , and . VLSID, page 391-394. IEEE Computer Society, (2017)Contact and junction engineering in bulk FinFET technology for improved ESD/latch-up performance with design trade-offs and its implications on hot carrier reliability., , , and . IRPS, page 3. IEEE, (2018)