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Disambiguation of "Kumar, Akash"

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A Self-Reconfiguring Cache Architecture to Improve Control Quality in Cyber-Physical Systems.

, , , , , and . ISORC, page 116-123. IEEE Computer Society, (2018)

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Akash Mehta

Akash Patwari

Hussein Ali Akash

Abdulrhman Ahmed Akasha

Podiyanachari Santhosh Kumar

 

Other publications of authors with the same name

NvMISC: Toward an FPGA-Based Emulation Platform for RISC-V and Nonvolatile Memories., , , and . IEEE Embed. Syst. Lett., 15 (4): 170-173 (December 2023)ReLAccS: A Multilevel Approach to Accelerator Design for Reinforcement Learning on FPGA-Based Systems., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (9): 1754-1767 (2021)Distributed resource management for concurrent execution of multimedia applications on MPSoC platforms., , , and . ICSAMOS, page 132-139. IEEE, (2011)Communication and migration energy aware design space exploration for multicore systems with intermittent faults., , and . DATE, page 1631-1636. EDA Consortium San Jose, CA, USA / ACM DL, (2013)A predictable communication assist., , , , , and . Conf. Computing Frontiers, page 97-98. ACM, (2010)PR-HMPSoC: A versatile partially reconfigurable heterogeneous Multiprocessor System-on-Chip for dynamic FPGA-based embedded systems., and . FPL, page 1-6. IEEE, (2014)Criticality-aware scrubbing mechanism for SRAM-based FPGAs., , , and . FPL, page 1-8. IEEE, (2014)Design and robust scheduling of nano-satellite swarm for synthetic aperture radar applications., , , and . ICARCV, page 705-710. IEEE, (2014)QoS-Aware Cross-Layer Reliability-Integrated FPGA-Based Dynamic Partially Reconfigurable System Partitioning., , , and . FPT, page 230-233. IEEE, (2018)ParaFRo: A hybrid parallel FPGA router using fine grained synchronization and partitioning., , and . FPL, page 1-11. IEEE, (2016)