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Disambiguation of "Blott, Michaela"

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Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs.

, , , , , , , , , , and . CoRR, (2018)

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Irene Blottner

Steffen Blottner

Stefan Blöttner

Annemarie Blottner

Gerhard Blottner

 

Other publications of authors with the same name

Machine Learning Aided Hardware Resource Estimation for FPGA DNN Implementations., , , and . IPDPS Workshops, page 77-83. IEEE, (2022)Memory-Efficient Dataflow Inference for Deep CNNs on FPGA., , , , , and . FPT, page 48-55. IEEE, (2020)Design of a flexible high-speed FPGA-based flow monitor for next generation networks., , , and . ICSAMOS, page 37-44. IEEE, (2010)A Hash Table for Line-Rate Data Processing., , , and . ACM Trans. Reconfigurable Technol. Syst., 8 (2): 13:1-13:15 (2015)Post-Training Quantization with Low-precision Minifloats and Integers on FPGAs., , , , , , and . CoRR, (2023)EcoFlow: Efficient Convolutional Dataflows on Low-Power Neural Network Accelerators., , , , , , , and . IEEE Trans. Computers, 73 (9): 2275-2289 (September 2024)Open-source FPGA-ML codesign for the MLPerf Tiny Benchmark., , , , , , , , , and 8 other author(s). CoRR, (2022)FAT: Training Neural Networks for Reliable Inference Under Hardware Faults., , , , and . ITC, page 1-10. IEEE, (2020)Designing scalable FPGA architectures using high-level synthesis., , and . PPoPP, page 403-404. ACM, (2018)DarwiNN: efficient distributed neuroevolution under communication constraints., , , and . GECCO Companion, page 141-142. ACM, (2020)