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Disambiguation of "Radway, Robert M."

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CHIMERA: A 0.92 TOPS, 2.2 TOPS/W Edge AI Accelerator with 2 MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference.

, , , , , , , , , , , , , , , , , and . VLSI Circuits, page 1-2. IEEE, (2021)

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Robert M Zoske

Robert M Gillenkirch

Robert M Stutz

Robert M Solomon

Robert M Fraunhoffer

 

Other publications of authors with the same name

Ultra-Dense 3D Physical Design Unlocks New Architectural Design Points with Large Benefits., , , , , , , , , and . DATE, page 1-6. IEEE, (2023)CHIMERA: A 0.92 TOPS, 2.2 TOPS/W Edge AI Accelerator with 2 MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference., , , , , , , , , and 8 other author(s). VLSI Circuits, page 1-2. IEEE, (2021)Testbench on a Chip: A Yield Test Vehicle for Resistive Memory Devices., , , , , , , , and . ISQED, page 1-7. IEEE, (2023)8-bit Transformer Inference and Fine-tuning for Edge Accelerators., , , , , and . ASPLOS (3), page 5-21. ACM, (2024)PBA: Percentile-Based Level Allocation for Multiple-Bits-Per-Cell RRAM., , , , , , and . ICCAD, page 1-9. IEEE, (2023)Thermal Scaffolding for Ultra-Dense 3D Integrated Circuits., , , , , , , and . DAC, page 1-6. IEEE, (2023)Foundry Monolithic 3D BEOL Transistor + Memory Stack: Iso-performance and Iso-footprint BEOL Carbon Nanotube FET+RRAM vs. FEOL Silicon FET+RRAM., , , , , , , , , and 1 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques., , , , , , , , , and 6 other author(s). ISSCC, page 226-228. IEEE, (2019)