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Logic Process Compatible 40nm 256K×144 Embedded RRAM with Low Voltage Current Limiter and Ambient Compensation Scheme to Improve the Read Window., , , , , , , , , и 4 other автор(ы). A-SSCC, стр. 13-16. IEEE, (2018)A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time., , , , , , , , и . ISSCC, стр. 434-436. IEEE, (2012)An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory., , , , , , , , , и 3 other автор(ы). ISSCC, стр. 206-208. IEEE, (2011)A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations., , , , , , , , , и 8 other автор(ы). ISSCC, стр. 1-3. IEEE, (2022)15.7 A 32Mb RRAM in a 12nm FinFet Technology with a 0.0249μm2 Bit-Cell, a 3.2GB/S Read Throughput, a 10KCycle Write Endurance and a 10-Year Retention at 105°C., , , , , , , , , и 7 other автор(ы). ISSCC, стр. 288-290. IEEE, (2024)Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros., , , , , , , , , и 1 other автор(ы). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (4): 1191-1205 (апреля 2024)A Nonvolatile Al-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM Compute-in-Memory Macro and 51.4-251TOPS/W., , , , , , , , , и 6 other автор(ы). ISSCC, стр. 258-259. IEEE, (2023)34.8 A 22nm 16Mb Floating-Point ReRAM Compute-in-Memory Macro with 31.2TFLOPS/W for AI Edge Devices., , , , , , , , , и 8 other автор(ы). ISSCC, стр. 580-582. IEEE, (2024)A 22nm 4Mb STT-MRAM Data-Encrypted Near-Memory Computation Macro with a 192GB/s Read-and-Decryption Bandwidth and 25.1-55.1TOPS/W 8b MAC for AI Operations., , , , , , , , , и 11 other автор(ы). ISSCC, стр. 178-180. IEEE, (2022)A 40nm 64kb 26.56TOPS/W 2.37Mb/mm2RRAM Binary/Compute-in-Memory Macro with 4.23x Improvement in Density and >75% Use of Sensing Dynamic Range., , , , , , и . ISSCC, стр. 1-3. IEEE, (2022)