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High Performance and Low Power Hardware Implementation for Cryptographic Hash Functions.

, , , and . IJDSN, (2014)

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The Implementation of a Power Efficient BCNN-Based Object Detection Acceleration on a Xilinx FPGA-SoC., and . iThings/GreenCom/CPSCom/SmartData, page 240-243. IEEE, (2019)Low cost and highly reliable hardened latch design for nanoscale CMOS technology., and . Microelectron. Reliab., 52 (6): 1209-1214 (2012)Low Power FPGA-SoC Design Techniques for CNN-based Object Detection Accelerator., and . UEMCON, page 1130-1134. IEEE, (2019)Prototyping circuit design for Dielectric Electroactive Polymers energy harvesting., , , , and . ISOCC, page 450-453. IEEE, (2011)Implementation of deep learning neural network for real-time object recognition in OpenCL framework., , , , and . ISOCC, page 298-299. IEEE, (2017)TDDB-based performance variation of combinational logic in deeply scaled CMOS technology., , and . ISQED, page 328-333. IEEE, (2012)Hardware-efficient parallel FIR digital filter structures for symmetric convolutions., and . ISCAS, page 2301-2304. IEEE, (2011)Effective algorithm for integrating clock gating and power gating to reduce dynamic and active leakage power simultaneously., , and . ISQED, page 74-79. IEEE, (2011)Artificial neural network implementation in FPGA: A case study., , and . ISOCC, page 297-298. IEEE, (2016)Novel 8-T CNFET SRAM cell design for the future ultra-low power microelectronics., , , and . ISOCC, page 243-244. IEEE, (2016)