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High Performance and Low Power Hardware Implementation for Cryptographic Hash Functions.

, , , и . IJDSN, (2014)

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Ken Lau

Ken Endo

Ken Herrmann

Ken Heydolph

Ken Eckstein

 

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Soft error tolerant latch design with low cost for nanoelectronic systems., и . ISCAS, стр. 1572-1575. IEEE, (2012)Hardware-efficient VLSI implementation for 3-parallel linear-phase FIR digital filter of odd length., и . ISCAS, стр. 998-1001. IEEE, (2012)Hardware-efficient parallel FIR digital filter structures for symmetric convolutions., и . ISCAS, стр. 2301-2304. IEEE, (2011)Artificial neural network implementation in FPGA: A case study., , и . ISOCC, стр. 297-298. IEEE, (2016)Novel 8-T CNFET SRAM cell design for the future ultra-low power microelectronics., , , и . ISOCC, стр. 243-244. IEEE, (2016)Effective algorithm for integrating clock gating and power gating to reduce dynamic and active leakage power simultaneously., , и . ISQED, стр. 74-79. IEEE, (2011)Power dissipation and area comparison of 512-bit and 1024-bit key AES., , , и . Comput. Math. Appl., 65 (9): 1378-1383 (2013)System Level Power Reduction for YOLO2 Sub-modules for Object Detection of Future Autonomous Vehicles., , , , , и . ISOCC, стр. 151-155. IEEE, (2018)Ultra-low power and high speed design and implementation of AES and SHA1 hardware cores in 65 nanometer CMOS technology., , и . EIT, стр. 405-410. IEEE, (2009)Unified Medium Access Control Architecture for Resource-Constrained Machine-to-Machine Devices., , , и . ACM Trans. Embed. Comput. Syst., 15 (2): 40:1-40:17 (2016)