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Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects.

, , , , , , , , , и . ATS, стр. 139-146. IEEE, (2006)

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Randa Kassab

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Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects., , , , , , , , , и . ATS, стр. 139-146. IEEE, (2006)Test Generation for Designs with On-Chip Clock Generators., и . Asian Test Symposium, стр. 411-417. IEEE Computer Society, (2009)Efficient Prognostication of Pattern Count with Different Input Compression Ratios., , , , , , , и . ETS, стр. 1-2. IEEE, (2020)X-Press Compactor for 1000x Reduction of Test Data., , , , , и . ITC, стр. 1-10. IEEE Computer Society, (2006)Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs., , , , , , , , , и 3 other автор(ы). ITC, стр. 1-10. IEEE, (2020)EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism., , , , , , и . ITC, стр. 1-9. IEEE Computer Society, (2011)Realizing High Test Quality Goals with Smart Test Resource Usage., , , , , , , и . ITC, стр. 525-533. IEEE Computer Society, (2004)Dynamic channel allocation for higher EDT compression in SoC designs., , , , , и . ITC, стр. 265-274. IEEE Computer Society, (2010)Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains., , , и . ITC, стр. 114-123. IEEE Computer Society, (2010)Test Compression Improvement with EDT Channel Sharing in SoC Designs., , , , , , , и . NATW, стр. 22-31. IEEE, (2014)