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Circuit and Methodology for Testing Small Delay Faults in the Clock Network., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (10): 2087-2097 (2018)Small delay testing for TSVs in 3-D ICs., , , , , , and . DAC, page 1031-1036. ACM, (2012)X-Sources Analysis for Improving the Test Quality.. ITC-Asia, page 121-126. IEEE, (2018)Built-in constraint resolution., , , and . ITC, page 10. IEEE Computer Society, (2005)Embedded Deterministic Test for Low-Cost Manufacturing Test., , , , , , , , , and 1 other author(s). ITC, page 301-310. IEEE Computer Society, (2002)Impact of Multiple-Detect Test Patterns on Product Quality., , , , , , , and . ITC, page 1031-1040. IEEE Computer Society, (2003)At-Speed Scan Test Method for the Timing Optimization and Calibration., , and . Asian Test Symposium, page 430-433. IEEE Computer Society, (2009)Compactor Independent Direct Diagnosis., , , , and . Asian Test Symposium, page 204-209. IEEE Computer Society, (2004)Test Coverage Analysis for Designs with Timing Exceptions., and . ATS, page 169-174. IEEE Computer Society, (2017)A Low Complexity Transmitter Architecture and Its Application to PAPR Reduction in SFBC MIMO-OFDM Systems., , and . ICC, page 1-5. IEEE, (2010)