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Disambiguation of "Rao, Rajeev"

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Detecting Privacy-Sensitive Code Changes with Language Modeling.

, , , , and . MSR, page 761-762. ACM, (2022)

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Rajeev Sudra

Rajeev Gangula

Rajeev Ranjan

Rajeev Kumar

Rajeev Kavety

 

Other publications of authors with the same name

Detecting Privacy-Sensitive Code Changes with Language Modeling., , , , and . MSR, page 761-762. ACM, (2022)Interactive AI Material Generation and Editing in NVIDIA Omniverse., , , , , , and . SIGGRAPH Real Time Live!, page 4:1-4:2. ACM, (2023)Soft error reduction in combinational logic using gate resizing and flipflop selection., , and . ICCAD, page 502-509. ACM, (2006)Circuit optimization techniques to mitigate the effects of soft errors in combinational logic., , , and . ACM Trans. Design Autom. Electr. Syst., 15 (1): 5:1-5:27 (2009)Statistical estimation of leakage current considering inter- and intra-die process variation., , , and . ISLPED, page 84-89. ACM, (2003)Modeling and Analysis of Parametric Yield under Power and Performance Constraints., , , and . IEEE Des. Test Comput., 22 (4): 376-385 (2005)Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation., , , , , , , , , and 1 other author(s). MICRO, page 7-18. IEEE Computer Society, (2003)Logic SER Reduction through Flipflop Redesign., , , and . ISQED, page 611-616. IEEE Computer Society, (2006)Leakage-and crosstalk-aware bus encoding for total power reduction., , , and . DAC, page 779-782. ACM, (2004)Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (3): 468-479 (2007)