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Systematic Design of Multi-Modulus/Multi-Function Residue Number System Processors., и . ISCAS, стр. 79-82. IEEE, (1994)Execution time comparison of lifting-based 2D wavelet transforms implementations on a VLIW DSP., , и . ISCAS, IEEE, (2006)An RNS barrett modular multiplication architecture., и . ISCAS, стр. 2229-2232. IEEE, (2014)Novel high-radix residue number system multipliers and adders., и . ISCAS (1), стр. 451-454. IEEE, (1999)Area-Throughput Trade-Offs for SHA-1 and SHA-256 Hash Functions' Pipelined Designs., , , , , и . Journal of Circuits, Systems, and Computers, 25 (4): 1650032:1-1650032:26 (2016)Outage probability of single carrier NOMA systems under I/Q imbalance., , , , , , и . WCNC, стр. 1-6. IEEE, (2018)A hybrid floating-point/logarithmic number system digital signal processor.. ICASSP, стр. 1079-1082. IEEE, (1989)A complex DSP processor using polynomial encoding., , и . ICASSP, стр. 1310-1313. IEEE, (1989)Approximate Logarithmic Multiplier For Convolutional Neural Network Inference With Computational Reuse., , , , , , , и . ICECS 2022, стр. 1-4. IEEE, (2022)Systematic design of full adder-based architectures for convolution., , , , и . ICASSP (1), стр. 389-392. IEEE Computer Society, (1993)