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A Time-Domain Computing-in-Memory based Processor using Predictable Decomposed Convolution for Arbitrary Quantized DNNs., , , , , , , , , and 5 other author(s). A-SSCC, page 1-4. IEEE, (2020)RNA: a reconfigurable architecture for hardware neural acceleration., , , , and . DATE, page 695-700. ACM, (2015)STC: Significance-aware Transform-based Codec Framework for External Memory Access Reduction., , , , , , and . DAC, page 1-6. IEEE, (2020)Exploiting Outer Loop Parallelism of Nested Loop on Coarse-Grained Reconfigurable Architectures., , , and . FCCM, page 32. IEEE Computer Society, (2014)Adaptive load balancing in mobile ad hoc networks., and . WCNC, page 1982-1987. IEEE, (2005)SURFEX: A 57fps 1080P resolution 220mW silicon implementation for simplified speeded-up robust feature with 65nm process., , , , , and . CICC, page 1-4. IEEE, (2013)A 65 nm uneven-dual-core SoC based platform for multi-device collaborative computing., , , , , , , and . ISCAS, page 2527-2530. IEEE, (2014)Bit-Level Disturbance-Aware Memory Partitioning for Parallel Data Access for MLC STT-RAM., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (11): 2345-2357 (2018)MoNA: Mobile Neural Architecture with Reconfigurable Parallel Dimensions., , , , and . NEWCAS, page 1-4. IEEE, (2019)Configuration approaches to improve computing efficiency of coarse-grained reconfigurable multimedia processor., , , , , and . FPL, page 1-4. IEEE, (2014)