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Disambiguation of "Esseni, David"

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Reducing the tunneling barrier thickness of bilayer ferroelectric tunnel junctions with metallic electrodes.

, , , , , , , and . DRC, page 1-2. IEEE, (2023)

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Wahyudi David

Florian Bodo David

Jens-Ulrich Davids

Joachim David

Heinz David

 

Other publications of authors with the same name

Reducing the Spike Rate in Deep Spiking Neural Networks., , and . ICONS, page 8:1-8:8. ACM, (2022)Operation and Design of Ferroelectric FETs for a BEOL Compatible Device Implementation., and . ESSDERC, page 215-218. IEEE, (2021)Reducing the spike rate of deep spiking neural networks based on time-encoding., , , and . Neuromorph. Comput. Eng., 4 (3): 34004 (2024)Supersteep retrograde doping in ferroelectric MOSFETs for sub-60mV/dec subthreshold swing., and . ESSDERC, page 360-363. IEEE, (2016)Strain engineering of single-layer MoS2., , , , and . ESSDERC, page 314-317. IEEE, (2015)Design of UWB LNA in 45nm CMOS technology: Planar bulk vs. FinFET., , , , , , and . ISCAS, page 2701-2704. IEEE, (2008)Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part II-Evaluation at Circuit Level and Design Perspectives., and . IEEE Trans. Very Large Scale Integr. Syst., 22 (12): 2499-2512 (2014)Performance study of strained III-V materials for ultra-thin body transistor applications., , , , , , , , , and 4 other author(s). ESSDERC, page 184-187. IEEE, (2016)Ferroelectric based FETs and synaptic devices for highly energy efficient computational technologies., , , , , and . CoRR, (2021)Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I - Device-Circuit Interaction and Evaluation at Device Level., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (12): 2488-2498 (2014)