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Disambiguation of "Parvais, Bertrand"

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Design of UWB LNA in 45nm CMOS technology: Planar bulk vs. FinFET.

, , , , , , and . ISCAS, page 2701-2704. IEEE, (2008)

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Bertrand Hirl

Bertrand Gloddek

Joachim Bertrand

Jessica Bertrand

Bertrand Malmendier

 

Other publications of authors with the same name

A low-power radio chipset in 40nm LP CMOS with beamforming for 60GHz high-data-rate wireless communication., , , , , , , , , and 4 other author(s). ISSCC, page 236-237. IEEE, (2013)Back-gate bias effect on UTBB-FDSOI non-linearity performance., , , , , , and . ESSDERC, page 148-151. IEEE, (2017)Reliability and Variability of Advanced CMOS Devices at Cryogenic Temperatures., , , , , , , , , and . IRPS, page 1-6. IEEE, (2020)A Composite AlGaN/cGaN Back Barrier for mm-Wave GaN-on-Si HEMTs., , , , , , , , and . ESSDERC, page 152-155. IEEE, (2023)A BSIM-Based Predictive Hot-Carrier Aging Compact Model., , , , , , , , , and . IRPS, page 1-9. IEEE, (2021)Migrating from planar to FinFET for further CMOS scaling: SOI or bulk?, , , , , , , , , and 9 other author(s). ESSCIRC, page 84-87. IEEE, (2009)FinFET RF receiver building blocks operating above 10 GHz., , , , , , , and . ESSCIRC, page 360-363. IEEE, (2009)A 40 nm LP CMOS PLL for high-speed mm-wave communication., , , , , , and . ESSCIRC, page 254-257. IEEE, (2010)FinFET technology for analog and RF circuits., , , , , , , and . ICECS, page 182-185. IEEE, (2007)Design of UWB LNA in 45nm CMOS technology: Planar bulk vs. FinFET., , , , , , and . ISCAS, page 2701-2704. IEEE, (2008)