Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Compiling HPC Kernels for the REDEFINE CGRA.

K. Madhu, S. Das, N. Sivanandan, S. Nandy, and R. Narayan. HPCC/CSS/ICESS, page 405-410. IEEE, (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Sivanandan, Nalesh

add a person with the name Sivanandan, Nalesh

Other publications of authors with the same name

Energy Aware Synthesis of Application Kernels Expressed in Functional Languages on a Coarse Grained Composable Reconfigurable Array.N. Sivanandan, K. Madhu, S. Das, S. Nandy, and R. Narayan. iNIS, page 7-12. IEEE, (2015)Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations.F. Merchant, A. Maity, M. Mahadurkar, K. Vatwani, I. Munje, M. C, N. Sivanandan, N. Gopalan, S. Raha, S. Nandy and 1 other author(s). VLSID, page 153-158. IEEE Computer Society, (2015)Two dimensional FFT architecture based on radix-43 algorithm with efficient output reordering.S. Kala, N. Sivanandan, B. Jose, J. Mathew, and M. Ottavi. DTIS, page 1-2. IEEE, (2018)Efficient Hardware Acceleration of Convolutional Neural Networks.S. Kala, B. Jose, J. Mathew, and N. Sivanandan. SoCC, page 191-192. IEEE, (2019)A Hardware-Software Co-design based Approach for Development of a Distributed DAQ System using FPGA.A. Krishnan, M. Supriya, and N. Sivanandan. VDAT, page 1-6. IEEE, (2021)Synthesis of Instruction Extensions on HyperCell, a reconfigurable datapath.K. Madhu, S. Das, M. C, N. Sivanandan, S. Nandy, and R. Narayan. ICSAMOS, page 215-224. IEEE, (2014)Design Space Exploration of Convolution Algorithms to Accelerate CNNs on FPGA.S. Kala, D. Paul, B. Jose, and N. Sivanandan. ISED, page 21-25. IEEE, (2018)UniWiG: Unified Winograd-GEMM Architecture for Accelerating CNN on FPGAs.S. Kala, J. Mathew, B. Jose, and N. Sivanandan. VLSID, page 209-214. IEEE, (2019)Energy Efficient, Scalable, and Dynamically Reconfigurable FFT Architecture for OFDM Systems.S. Kala, N. Sivanandan, S. Nandy, and R. Narayan. ISED, page 20-24. IEEE Computer Society, (2014)High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit.S. Kala, N. Sivanandan, A. Maity, S. Nandy, and R. Narayan. ISCAS, page 3034-3037. IEEE, (2013)

BibSonomy

Disambiguation of "Sivanandan, Nalesh"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Compiling HPC Kernels for the REDEFINE CGRA.

Please choose a person to relate this publication to

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Sivanandan, Nalesh"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Compiling HPC Kernels for the REDEFINE CGRA.

Please choose a person to relate this publication to

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Compiling HPC Kernels for the REDEFINE CGRA.