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A low latency and low power dynamic Carry Save Adder., , , , , , , and . ISCAS (2), page 477-480. IEEE, (2004)Performance and power evaluation of an in-line accelerator., , , , , and . Conf. Computing Frontiers, page 81-82. ACM, (2010)A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons., , , , , , , , , and 1 other author(s). CICC, page 1-4. IEEE, (2011)IBM second-generation RISC machine organization., , , , , , , , , and 3 other author(s). ICCD, page 138-142. IEEE, (1989)Custom is from Venus and synthesis from Mars., , , , , and . DAC, page 992. ACM, (2008)1 Mb 0.41 µm2 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing., , , and . IEEE J. Solid State Circuits, 49 (4): 896-907 (2014)Matrix-matrix multiplication on a large register file architecture with indirection., , , and . HiPC, page 1-10. IEEE Computer Society, (2014)IBM second-generation RISC machine organization., , , , , , , , , and 3 other author(s). Compcon, page 173-178. IEEE Computer Society, (1990)Processor architecture for software implementation of multi-sector G-RAKE receivers for HSUPA wireless infrastructure., , , , , and . ICASSP, page 2770-2774. IEEE, (2013)Architectural perspectives of future wireless base stations based on the IBM PowerEN™ processor., , , , , , and . HPCA, page 423-432. IEEE Computer Society, (2012)