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A 800-Mb/s 0.89-pJ/b reference-less optical receiver with pulse-position-modulation scheme., , , и . ISCAS, стр. 2346-2349. IEEE, (2016)A 20-Gb/s 1.27pJ/b low-power optical receiver front-end in 65nm CMOS., , , и . ISCAS, стр. 1492-1495. IEEE, (2014)A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line., , , , , и . ESSCIRC, стр. 447-450. IEEE, (2014)Reference Spur Reduction Techniques for a Phase-Locked Loop., , , и . IEEE Access, (2019)A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS., , , , , , и . ISCAS, стр. 2389-2392. IEEE, (2015)20-Gb/s 5-VPP and 25-Gb/s 3.8-VPP Area-Efficient Modulator Drivers in 65-nm CMOS., , , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (11): 1034-1038 (2016)An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection., , , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 62-II (9): 836-840 (2015)A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process., , , , , , , и . IEEE J. Solid State Circuits, 50 (11): 2603-2612 (2015)A Crystal-Less Programmable Clock Generator with RC-LC Hybrid Oscillator for GHz Applications in 14 nm FinFET CMOS., , , , , и . BCICTS, стр. 263-266. IEEE, (2018)A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process., , , , , и . A-SSCC, стр. 101-104. IEEE, (2014)