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A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS.

K. Park, W. Bae, H. Ju, J. Lee, G. Jeong, Y. Kim, and D. Jeong. ISCAS, page 2389-2392. IEEE, (2015)

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Jin-Woo Bae

Seong-Woo Bae

Ulrich Rhamm

Gérard de Rham

Soonil Bae

Other publications of authors with the same name

A 10-Gb/s 6-Vpp differential modulator driver in 65-nm CMOS.Y. Kim, W. Bae, and D. Jeong. ISCAS, page 1869-1872. IEEE, (2014)A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control.K. Park, W. Bae, and D. Jeong. CICC, page 1-4. IEEE, (2017)BAG2: A process-portable framework for generator-based AMS circuit design.E. Chang, J. Han, W. Bae, Z. Wang, N. Narevsky, B. Nikolic, and E. Alon. CICC, page 1-8. IEEE, (2018)4.3 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET.C. Schmidt, J. Wright, Z. Wang, E. Chang, A. Ou, W. Bae, S. Huang, A. Flynn, B. Richards, K. Asanovic and 2 other author(s). ISSCC, page 58-60. IEEE, (2021)A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET.S. Bailey, J. Han, P. Rigge, R. Lin, E. Chang, H. Mao, Z. Wang, C. Markley, A. Izraelevitz, A. Wang and 21 other author(s). A-SSCC, page 285-288. IEEE, (2018)A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection.S. Cho, S. Kim, M. Choo, H. Ko, J. Lee, W. Bae, and D. Jeong. IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (9): 2691-2702 (2018)A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection.S. Cho, S. Kim, M. Choo, J. Lee, H. Ko, S. Jang, S. Chu, W. Bae, Y. Kim, and D. Jeong. ESSCIRC, page 384-387. IEEE, (2015)A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm.G. Jeong, S. Chu, Y. Kim, S. Jang, S. Kim, W. Bae, S. Cho, H. Ju, and D. Jeong. A-SSCC, page 1-4. IEEE, (2015)A low-power pulse position modulation transceiver.W. Bae, C. Yoon, and D. Jeong. ISCAS, page 1614-1617. IEEE, (2015)A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS.W. Bae, H. Ju, K. Park, S. Cho, and D. Jeong. A-SSCC, page 1-4. IEEE, (2015)

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Disambiguation of "Bae, Woo-Rham"

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A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS.

Please choose a person to relate this publication to

Jin-Woo Bae

Seong-Woo Bae

Ulrich Rhamm

Gérard de Rham

Soonil Bae

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Bae, Woo-Rham"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS.

Please choose a person to relate this publication to

Jin-Woo Bae

Seong-Woo Bae

Ulrich Rhamm

Gérard de Rham

Soonil Bae

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS.