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Disambiguation of "Ju, Haram"

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A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS.

, , , , , , and . ISCAS, page 2389-2392. IEEE, (2015)

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Tomi Haramina

Tatjana Haramina

Anna-Pavlina Haramis

Chandrashekara Rajashekara Haramagatti

Zhaojie Ju

 

Other publications of authors with the same name

A 6-to-32 Gb/s voltage-mode transmitter with scalable supply, voltage swing, and pre-emphasis in 65-nm CMOS., , , and . A-SSCC, page 241-244. IEEE, (2016)A Supply-Scalable-Serializing Transmitter With Controllable Output Swing and Equalization for Next-Generation Standards., , , , and . IEEE Trans. Ind. Electron., 65 (7): 5979-5989 (2018)A 64 GB/s 1.5 PJ/Bit PAM-4 Transmitter with 3-Tap FFE and GM-Regulated Active-Feedback Driver in 28 NM CMOS., , , and . VLSI Circuits, page 51-52. IEEE, (2018)A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS., , , , and . A-SSCC, page 1-4. IEEE, (2015)A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- Gm Bias., , , , , , , , and . IEEE J. Solid State Circuits, 51 (10): 2312-2327 (2016)A Design of Data Path Based on CMOS Logic for a 72-Gb/s PAM-4 Transmitter in 28-nm CMOS., , , and . ICEIC, page 1-4. IEEE, (2019)A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS., , , , , , and . ISCAS, page 2389-2392. IEEE, (2015)A 800-Mb/s 0.89-pJ/b reference-less optical receiver with pulse-position-modulation scheme., , , and . ISCAS, page 2346-2349. IEEE, (2016)A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm., , , , , , , , and . A-SSCC, page 1-4. IEEE, (2015)A 48Gb/s 2.4pJ/b PAM-4 Baud-Rate Digital CDR with Stochastic Phase Detection Technique in 40nm CMOS., , , and . A-SSCC, page 1-3. IEEE, (2021)