Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS.

K. Park, W. Bae, H. Ju, J. Lee, G. Jeong, Y. Kim, and D. Jeong. ISCAS, page 2389-2392. IEEE, (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Rolf Gyufko

Andrea Gyulai-Schmidt

Agnes Gyulay

Adam Gyürki Kis

Su-Jeong Jeong

Other publications of authors with the same name

A 0.015-mm2 Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology.G. Jeong, W. Kim, J. Park, T. Kim, H. Park, and D. Jeong. IEEE Trans. Circuits Syst. II Express Briefs, 64-II (6): 655-659 (2017)A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process.S. Chu, W. Bae, G. Jeong, J. Joo, G. Kim, and D. Jeong. A-SSCC, page 101-104. IEEE, (2014)A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- Gm Bias.G. Jeong, S. Chu, Y. Kim, S. Jang, S. Kim, W. Bae, S. Cho, H. Ju, and D. Jeong. IEEE J. Solid State Circuits, 51 (10): 2312-2327 (2016)A Crystal-Less Programmable Clock Generator with RC-LC Hybrid Oscillator for GHz Applications in 14 nm FinFET CMOS.J. Hwang, G. Jeong, S. Chu, W. Kim, T. Kim, and D. Jeong. BCICTS, page 263-266. IEEE, (2018)Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection.G. Jeong, W. Bae, and D. Jeong. Sensors, 17 (9): 1962 (2017)A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS.K. Park, W. Bae, H. Ju, J. Lee, G. Jeong, Y. Kim, and D. Jeong. ISCAS, page 2389-2392. IEEE, (2015)A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line.W. Bae, G. Jeong, K. Park, S. Cho, Y. Kim, and D. Jeong. ESSCIRC, page 447-450. IEEE, (2014)An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection.S. Jang, S. Kim, S. Chu, G. Jeong, Y. Kim, and D. Jeong. IEEE Trans. Circuits Syst. II Express Briefs, 62-II (9): 836-840 (2015)20-Gb/s 5-VPP and 25-Gb/s 3.8-VPP Area-Efficient Modulator Drivers in 65-nm CMOS.Y. Kim, G. Jeong, J. Park, J. Park, G. Kim, and D. Jeong. IEEE Trans. Circuits Syst. II Express Briefs, 63-II (11): 1034-1038 (2016)A 32 Gb/s, 201 mW, MZM/EAM Cascode Push-Pull CML Driver in 65 nm CMOS.J. Hwang, G. Jeong, W. Bae, J. Park, C. Yoon, J. Yoon, J. Joo, G. Kim, and D. Jeong. IEEE Trans. Circuits Syst. II Express Briefs, 65-II (4): 436-440 (2018)

BibSonomy

Disambiguation of "Jeong, Gyu-Seob"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS.

Please choose a person to relate this publication to

Rolf Gyufko

Andrea Gyulai-Schmidt

Agnes Gyulay

Adam Gyürki Kis

Su-Jeong Jeong

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Jeong, Gyu-Seob"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS.

Please choose a person to relate this publication to

Rolf Gyufko

Andrea Gyulai-Schmidt

Agnes Gyulay

Adam Gyürki Kis

Su-Jeong Jeong

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS.