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A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding.

J. Zhou, D. Zhou, S. Wang, S. Zhang, T. Yoshimura, and S. Goto. IEEE Trans. Very Large Scale Integr. Syst., 25 (2): 714-724 (2017)

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Zhou Zhou

Yaming Zhou

Rui Zhou

Jun Zhou

Other publications of authors with the same name

Merge mode based fast inter prediction for HEVC.Z. Cheng, H. Sun, D. Zhou, and S. Kimura. VCIP, page 1-4. IEEE, (2015)Approximate-DCT-Derived Measurement Matrices with Row-Operation-Based Measurement Compression and its VLSI Architecture for Compressed Sensing.J. Zhou, D. Zhou, T. Yoshimura, and S. Goto. IEICE Trans. Electron., 101-C (4): 263-272 (2018)A Low-Power VLSI Architecture for HEVC De-Quantization and Inverse Transform.H. Sun, D. Zhou, S. Zhang, and S. Kimura. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 99-A (12): 2375-2387 (2016)A High Performance HEVC De-Blocking Filter and SAO Architecture for UHDTV Decoder.J. Zhu, D. Zhou, and S. Goto. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (12): 2612-2622 (2013)A High Performance and Low Bandwidth Multi-Standard Motion Compensation Design for HD Video Decoder.X. Chen, P. Liu, D. Zhou, J. Zhu, X. Pan, and S. Goto. IEICE Trans. Electron., 93-C (3): 253-260 (2010)Low-Power Motion Estimation Processor with 3D Stacked Memory.S. Zhang, J. Zhou, D. Zhou, S. Kimura, and S. Goto. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 98-A (7): 1431-1441 (2015)Alternating asymmetric search range assignment for bidirectional motion estimation in H.265/HEVC and H.264/AVC.J. Zhou, D. Zhou, and S. Goto. J. Vis. Commun. Image Represent., 25 (5): 1275-1286 (2014)An area-efficient 4/8/16/32-point inverse DCT architecture for UHDTV HEVC decoder.H. Sun, D. Zhou, J. Zhu, S. Kimura, and S. Goto. VCIP, page 197-200. IEEE, (2014)An independent bandwidth reduction device for HEVC VLSI video system.J. Zhu, L. Guo, D. Zhou, S. Kimura, and S. Goto. ISCAS, page 609-612. IEEE, (2015)Interlaced asymmetric search range assignment for bidirectional motion estimation.J. Zhou, D. Zhou, and S. Goto. ICIP, page 1557-1560. IEEE, (2012)

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Disambiguation of "Zhou, Dajiang"

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A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding.

Please choose a person to relate this publication to

Zhou Zhou

Zhou Zhou

Yaming Zhou

Rui Zhou

Jun Zhou

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Zhou, Dajiang"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding.

Please choose a person to relate this publication to

Zhou Zhou

Zhou Zhou

Yaming Zhou

Rui Zhou

Jun Zhou

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding.