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Efficient Machine Learning on Encrypted Data Using Hyperdimensional Computing., , , , , , , and . ISLPED, page 1-6. IEEE, (2023)A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 46 (1): 194-208 (2011)MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP., , , , and . MICRO, page 305-316. IEEE Computer Society, (2012)Efficiently prefetching complex address patterns., , , , , and . MICRO, page 141-152. ACM, (2015)Kill the Program Counter: Reconstructing Program Behavior in the Processor Cache Hierarchy., , , , , and . ASPLOS, page 737-749. ACM, (2017)Improving cache performance using read-write partitioning., , , , and . HPCA, page 452-463. IEEE Computer Society, (2014)Improving DRAM performance by parallelizing refreshes with accesses., , , , , , and . HPCA, page 356-367. IEEE Computer Society, (2014)The heterogeneous block architecture., , and . ICCD, page 386-393. IEEE Computer Society, (2014)Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance., , , , , , , and . ISSCC, page 402-403. IEEE, (2008)Flexible associativity for DRAM caches., , , , and . CF, page 88-96. ACM, (2018)