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A 11.1-to-14.2 GHz Self-adapted Two-point Modulation Dual-path Type-II Digital PLL Concurrently Achieving 124.7-MHz/μs Chirp Rate and 2.27-GHz Bandwidth.

W. Deng, Z. Chen, H. Jia, S. Sun, G. Chen, Z. Wang, and B. Chi. VLSI Circuits, page 1-2. IEEE, (2021)

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Jia Jia

Jia Xu

Lina Jia

Jia Miao

Jia Zeng

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International Solid-State Circuits Conference 2019 aims at "envisioning the future".H. Jia, and B. Chi. Sci. China Inf. Sci., 62 (6): 67401:1-67401:2 (2019)An 8.2-to-21.5 GHz Dual-Core Quad-Mode Orthogonal-Coupled VCO with Concurrently Dual-Output using Parallel 8-Shaped Resonator.W. Deng, H. Jia, R. Wu, S. Sun, C. Li, Z. Wang, and B. Chi. CICC, page 1-2. IEEE, (2021)A Compact E-Band Load-Modulation Balanced Power Amplifier Using Coupled Transmission-Line Output Network Achieving 22.1-dBm Psat and 34.9%/12.2% Efficiency at Psat/6-dB PBO.X. Huang, H. Jia, W. Deng, Z. Wang, and B. Chi. A-SSCC, page 1-3. IEEE, (2023)An Enhanced Class-F Dual-Core VCO With Common-Mode-Noise Self-Cancellation and Isolation Technique.Q. Wu, W. Deng, Y. Sun, H. Jia, H. Liu, S. Zhang, Z. Wang, and B. Chi. IEEE J. Solid State Circuits, 59 (8): 2441-2454 (August 2024)A Fully Integrated QPSK/16-QAM D-Band CMOS Transceiver With Mixed-Signal Baseband Circuitry Realizing Digital Interfaces.P. Guan, R. Ma, H. Jia, W. Deng, M. Deng, J. Xue, A. Yan, S. Sun, Q. Peng, T. Siriburanon and 3 other author(s). IEEE J. Solid State Circuits, 59 (10): 3123-3141 (October 2024)An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope.A. Yan, W. Deng, H. Jia, S. Sun, C. Tang, B. Zhu, Y. Fu, H. Liu, and B. Chi. VLSI Technology and Circuits, page 1-2. IEEE, (2023)A 122-168GHz Radar/Communication Fusion-Mode Transceiver with 30GHz Chirp Bandwidth, 13dBm Psat, and 8.3dBm OP1dB in 28nm CMOS.Z. Chen, W. Deng, H. Jia, P. Guan, T. Ma, S. Sun, X. Huang, G. Chen, R. Ma, S. Dong and 3 other author(s). VLSI Circuits, page 1-2. IEEE, (2021)A 4.8-GHz Time-Interleaved Multi-Reference PLL with 16.1-fs Jitter.H. Liu, W. Deng, H. Jia, S. Zhang, S. Sun, and B. Chi. ESSCIRC, page 261-264. IEEE, (2023)A 44-52 GHz Reflection-type Phase Shifter with 1.4° Phase Resolution in 28nm CMOS Process.S. Dong, Z. Chen, H. Jia, W. Deng, and B. Chi. ICTA, page 15-16. IEEE, (2020)Optimization methods for high inductance-density inductors for high speed integrated circuits.Z. Dang, H. Jia, W. Deng, Z. Wang, and B. Chi. ICTA, page 243-244. IEEE, (2021)

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Disambiguation of "Jia, Haikun"

Please choose a person to relate this publication to

Jia Jia

Jia Xu

Lina Jia

Jia Miao

Jia Zeng

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Jia, Haikun"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 11.1-to-14.2 GHz Self-adapted Two-point Modulation Dual-path Type-II Digital PLL Concurrently Achieving 124.7-MHz/μs Chirp Rate and 2.27-GHz Bandwidth.

Please choose a person to relate this publication to

Jia Jia

Jia Xu

Lina Jia

Jia Miao

Jia Zeng

Other publications of authors with the same name

Disambiguation