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Disambiguation of "Parisi, Angelo"

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A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter.

, , , , , , , , , , , , , and . ISSCC, page 445-447. IEEE, (2021)

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Jürgen Parisi

Jürgen Parisi

Jürgen Parisi

Giovanni Parisi

Jürgen Parisi

 

Other publications of authors with the same name

32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays., , , , , , , , , and 5 other author(s). ISSCC, page 456-458. IEEE, (2021)A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter., , , , , , , , , and 4 other author(s). ISSCC, page 445-447. IEEE, (2021)Digitally assisted frequency synthesizers and data converters for wide-band radio systems.. Polytechnic University of Milan, Italy, (2022)17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking., , , , , , , and . ISSCC, page 268-270. IEEE, (2020)17.5 A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter., , , , , , , and . ISSCC, page 274-276. IEEE, (2020)A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity., , , and . ICECS, page 1-4. IEEE, (2021)A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters., , , , , , , , and . NEWCAS, page 20-24. IEEE, (2022)