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Disambiguation of "Karl, Eric"

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Session 24 Overview: Advanced Embedded Memories Memory Subcommittee.

, , and . ISSCC, page 332-333. IEEE, (2021)

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Karl Eric Thonner

Ull Erich

Hauke Erichsen

Gerda Erich

Klaus Erichson

 

Other publications of authors with the same name

Timing error correction techniques for voltage-scalable on-chip memories., , and . ISCAS (4), page 3563-3566. IEEE, (2005)Advances in Microprocessor Cache Architectures Over the Last 25 Years., , , , , , , , and . IEEE Micro, 41 (6): 78-88 (2021)A 10nm SRAM Design using Gate-Modulated Self-Collapse Write Assist Enabling 175mV VMIN Reduction with Negligible Power Overhead., , , , , , , and . VLSI Circuits, page 1-2. IEEE, (2020)A High Output Power 1V Charge Pump and Power Switch for Configurable, In-Field-Programmable Metal eFuse on Intel 4 Logic Technology., , , , , , , and . VLSI Technology and Circuits, page 136-137. IEEE, (2022)15.2 A 2048x60m4 SRAM Design in Intel 4 with an Around-the-Array Power-Delivery Scheme Using PowerVia., , , , , , , , , and 3 other author(s). ISSCC, page 278-280. IEEE, (2024)SE1: What Technologies Will Shape the Future of Computing?, , , , , , , , , and . ISSCC, page 537-538. IEEE, (2021)17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology., , , , , , and . ISSCC, page 308-309. IEEE, (2016)17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology., , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)A 23.6Mb/mm2 SRAM in 10nm FinFET technology with pulsed PMOS TVC and stepped-WL for low-voltage applications., , , , , and . ISSCC, page 196-198. IEEE, (2018)A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products., , , , , , , , , and 24 other author(s). VLSIC, page 12-. IEEE, (2015)