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Session 24 Overview: Advanced Embedded Memories Memory Subcommittee.

E. Karl, S. Shiratake, и J. Chang. ISSCC, стр. 332-333. IEEE, (2021)

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Karl Eric Thonner

Friederike Erichsen-Wendt

Claus Erichsen

Kay Erichsen

Curt Erich

Другие публикации лиц с тем же именем

Timing error correction techniques for voltage-scalable on-chip memories.E. Karl, D. Sylvester, и D. Blaauw. ISCAS (4), стр. 3563-3566. IEEE, (2005)Advances in Microprocessor Cache Architectures Over the Last 25 Years.R. Iyer, V. De, R. Illikkal, D. Koufaty, B. Chitlur, A. Herdrich, M. Khellah, F. Hamzaoglu, и E. Karl. IEEE Micro, 41 (6): 78-88 (2021)A 10nm SRAM Design using Gate-Modulated Self-Collapse Write Assist Enabling 175mV VMIN Reduction with Negligible Power Overhead.Z. Guo, J. Wiedemer, Y. Kim, P. Ramamoorthy, P. Sathyaprasad, S. Shridharan, D. Kim, и E. Karl. VLSI Circuits, стр. 1-2. IEEE, (2020)17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology.J. Keane, J. Kulkarni, K. Koo, S. Nalam, Z. Guo, E. Karl, и K. Zhang. ISSCC, стр. 308-309. IEEE, (2016)17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology.E. Karl, Z. Guo, J. Conary, J. Miller, Y. Ng, S. Nalam, D. Kim, J. Keane, U. Bhattacharya, и K. Zhang. ISSCC, стр. 1-3. IEEE, (2015)A 23.6Mb/mm2 SRAM in 10nm FinFET technology with pulsed PMOS TVC and stepped-WL for low-voltage applications.Z. Guo, D. Kim, S. Nalam, J. Wiedemer, X. Wang, и E. Karl. ISSCC, стр. 196-198. IEEE, (2018)A High Output Power 1V Charge Pump and Power Switch for Configurable, In-Field-Programmable Metal eFuse on Intel 4 Logic Technology.S. Hutchins, J. Li, A. Sanne, Z. Chen, M. Hasan, U. Bhattacharya, E. Karl, и J. Kulkarni. VLSI Technology and Circuits, стр. 136-137. IEEE, (2022)15.2 A 2048x60m4 SRAM Design in Intel 4 with an Around-the-Array Power-Delivery Scheme Using PowerVia.D. Kim, Y. Kim, A. Shrivastava, G. Park, A. Pillai, K. Bannore, T. Doan, M. Rahman, G. Baek, C. Ong и 3 other автор(ы). ISSCC, стр. 278-280. IEEE, (2024)SE1: What Technologies Will Shape the Future of Computing?H. Mair, S. Shiratake, E. Karl, T. Burd, J. Chang, D. Marr, S. Naffziger, H. Corporaal, K. Takeuchi, и N. Shanbhag. ISSCC, стр. 537-538. IEEE, (2021)A 23.6-Mb/mm $^2$ SRAM in 10-nm FinFET Technology With Pulsed-pMOS TVC and Stepped-WL for Low-Voltage Applications.Z. Guo, D. Kim, S. Nalam, J. Wiedemer, X. Wang, и E. Karl. IEEE J. Solid State Circuits, 54 (1): 210-216 (2019)

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