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Machine Learning Techniques in Analog Layout Automation.

T. Dhar, K. Kunal, Y. Li, Y. Lin, M. Madhusudan, J. Poojary, A. Sharma, S. Burns, R. Harjani, J. Hu, P. Mukherjee, S. Yaldiz, и S. Sapatnekar. ISPD, стр. 71-72. ACM, (2021)

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Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays.N. Karmokar, A. Sharma, J. Poojary, M. Madhusudan, R. Harjani, и S. Sapatnekar. DATE, стр. 166-171. IEEE, (2022)The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk).T. Dhar, K. Kunal, Y. Li, Y. Lin, M. Madhusudan, J. Poojary, A. Sharma, S. Burns, R. Harjani, J. Hu и 3 other автор(ы). ICCAD, стр. 54:1-54:2. IEEE, (2020)Machine Learning Techniques in Analog Layout Automation.T. Dhar, K. Kunal, Y. Li, Y. Lin, M. Madhusudan, J. Poojary, A. Sharma, S. Burns, R. Harjani, J. Hu и 3 other автор(ы). ISPD, стр. 71-72. ACM, (2021)Aging of Current DACs and its Impact in Equalizer Circuits.T. Dhar, J. Poojary, R. Harjani, и S. Sapatnekar. IRPS, стр. 1-6. IEEE, (2021)Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models.T. Dhar, J. Poojary, Y. Li, K. Kunal, M. Madhusudan, A. Sharma, S. Manasi, J. Hu, R. Harjani, и S. Sapatnekar. ASP-DAC, стр. 158-163. ACM, (2021)Analog/Mixed-Signal Layout Optimization using Optimal Well Taps.R. S, M. Madhusudan, A. Sharma, J. Poojary, S. Yaldiz, R. Harjani, S. Burns, и S. Sapatnekar. ISPD, стр. 159-166. ACM, (2022)GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits.K. Kunal, T. Dhar, M. Madhusudan, J. Poojary, A. Sharma, W. Xu, S. Burns, J. Hu, R. Harjani, и S. Sapatnekar. DATE, стр. 55-60. IEEE, (2020)Understanding Distance-Dependent Variations for Analog Circuits in a FinFET Technology.M. Madhusudan, J. Poojary, A. Sharma, R. S, K. Kunal, S. Sapatnekar, и R. Harjani. ESSDERC, стр. 69-72. IEEE, (2023)A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement.T. Dhar, R. S, J. Poojary, S. Yaldiz, S. Burns, R. Harjani, и S. Sapatnekar. DATE, стр. 148-153. IEEE, (2022)A general approach for identifying hierarchical symmetry constraints for analog circuit layout.K. Kunal, J. Poojary, T. Dhar, M. Madhusudan, R. Harjani, и S. Sapatnekar. ICCAD, стр. 120:1-120:8. IEEE, (2020)

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