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A TCAD Compatible SONOS Trapping Layer Model for Accurate Programming Dynamics., , , , , , , , and . IMW, page 1-4. IEEE, (2021)Development of Gated Pinned Avalanche Photodiode Pixels for High-Speed Low-Light Imaging., , , , , , and . Sensors, 16 (8): 1294 (2016)Gate Side Injection Operating Mode for 3D NAND Flash Memories., , , , , , , , and . IMW, page 1-4. IEEE, (2024)Characterization of charge trapping in SiO2/Al2O3 dielectric stacks by pulsed C-V technique., , , , and . Microelectron. Reliab., 47 (4-5): 508-512 (2007)Optimization of Retention in Ferroelectricity Boosted Gate Stacks for 3D NAND., , , , , , , and . IMW, page 1-4. IEEE, (2023)At the Extreme of 3D-NAND Scaling: 25 nm Z-Pitch with 10 nm Word Line Cells., , , , , , , , and . IMW, page 1-4. IEEE, (2022)Improved MW of IGZO-channel FeFET by Reading Scheme Optimization and Interfacial Engineering., , , , , , , , , and . IMW, page 1-4. IEEE, (2023)High-K incorporated in a SiON tunnel layer for 3D NAND programming voltage reduction., , , , , , , , and . IMW, page 1-4. IEEE, (2022)Liquid Memory and the Future of Data Storage., , , , , , , , , and 6 other author(s). IMW, page 1-4. IEEE, (2022)Enabling 3D NAND Trench Cells for Scaled Flash Memories., , , , , , , , and . IMW, page 1-4. IEEE, (2023)