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A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS., , , , , , , , and . CICC, page 1-4. IEEE, (2012)A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS., , , , , , , , , and 5 other author(s). ISSCC, page 213-222. IEEE, (2006)Multi-Wavelength Optical Transceivers Integrated on Node (MOTION)., , , , , , , , , and 11 other author(s). OFC, page 1-3. IEEE, (2019)A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop., , , , , , , and . CICC, page 81-84. IEEE, (2003)A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS., , , , , , , , , and 5 other author(s). CICC, page 1-4. IEEE, (2012)A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS., , , , , , , and . ISSCC, page 368-369. IEEE, (2009)A 7Gb/s 9.3mW 2-Tap Current-Integrating DFE Receiver., , , and . ISSCC, page 230-599. IEEE, (2007)22.1 A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networks., , , , , , , , , and 1 other author(s). ISSCC, page 1-3. IEEE, (2015)A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS., , , , , , and . ISSCC, page 122-124. IEEE, (2019)3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI., , , , , , , , , and 1 other author(s). ISSCC, page 56-57. IEEE, (2016)