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Disambiguation of "Sadhu, Bodhisatwa"

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A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS.

, , , , , , , , , , , , , , and . CICC, page 1-4. IEEE, (2012)

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Ayan Sadhu

Jhuma Sadhukan

Veera Bhadraiah Sadhu

 

Other publications of authors with the same name

A 250-mW 60-GHz CMOS Transceiver SoC Integrated With a Four-Element AiP Providing Broad Angular Link Coverage., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 55 (6): 1516-1529 (2020)Session 14 Overview: mm-Wave Transceivers for Communication and Radar Wireless Subcommittee., , and . ISSCC, page 216-217. IEEE, (2021)An 8GHz multi-beam spatio-spectral beamforming receiver using an all-passive discrete time analog baseband in 65nm CMOS., , , , , and . CICC, page 1-4. IEEE, (2012)7.2 A 28GHz 32-element phased-array transceiver IC with concurrent dual polarized beams and 1.4 degree beam-steering resolution for 5G communication., , , , , , , , , and 10 other author(s). ISSCC, page 128-129. IEEE, (2017)Analysis and Design of a 5 GS/s Analog Charge-Domain FFT for an SDR Front-End in 65 nm CMOS., , , and . IEEE J. Solid State Circuits, 48 (5): 1199-1211 (2013)An Integral Path Self-Calibration Scheme for a Dual-Loop PLL., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 48 (4): 996-1008 (2013)An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS., , , , , , , , , and 1 other author(s). VLSIC, page 176-177. IEEE, (2012)Capacitor bank design for wide tuning range LC VCOs: 850MHz-7.1GHz (157%)., and . ISCAS, page 1975-1978. IEEE, (2010)10.8 A 12-to-26GHz fractional-N PLL with dual continuous tuning LC-D/VCOs., , , , and . ISSCC, page 196-198. IEEE, (2016)Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion., , , , , , , , , and 4 other author(s). CICC, page 1-4. IEEE, (2013)