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Virtual-to-Physical address translation for an FPGA-based interconnect with host and GPU remote DMA capabilities.

R. Ammendola, A. Biagioni, O. Frezza, F. Cicero, A. Lonardo, P. Paolucci, D. Rossetti, F. Simula, L. Tosoratto, and P. Vicini. FPT, page 58-65. IEEE, (2013)

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Ottorino Mazzetta

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Design and implementation of a modular, low latency, fault-aware, FPGA-based network interface.R. Ammendola, A. Biagioni, O. Frezza, F. Cicero, A. Lonardo, P. Paolucci, D. Rossetti, F. Simula, L. Tosoratto, and P. Vicini. ReConFig, page 1-6. IEEE, (2013)Distributed simulation of polychronous and plastic spiking neural networks: strong and weak scaling of a representative mini-application benchmark executed on a small-scale commodity cluster.P. Paolucci, R. Ammendola, A. Biagioni, O. Frezza, F. Cicero, A. Lonardo, E. Pastorelli, F. Simula, L. Tosoratto, and P. Vicini. CoRR, (2013)'Mutual Watch-dog Networking': Distributed Awareness of Faults and Critical Events in Petascale/Exascale systems.R. Ammendola, A. Biagioni, O. Frezza, F. Cicero, A. Lonardo, P. Paolucci, D. Rossetti, F. Simula, L. Tosoratto, and P. Vicini. CoRR, (2013)RED-SEA: Network Solution for Exascale Architectures.A. Biagioni, P. Cretaro, O. Frezza, F. Cicero, A. Lonardo, M. Martinelli, P. Paolucci, E. Pastorelli, F. Simula, M. Turisini and 58 other author(s). DSD, page 712-719. IEEE, (2022)TEXTAROSSA: Towards EXtreme scale Technologies and Accelerators for euROhpc hw/Sw Supercomputing Applications for exascale.G. Agosta, D. Cattaneo, W. Fornaciari, A. Galimberti, G. Massari, F. Reghenzani, F. Terraneo, D. Zoni, C. Brandolese, M. Celino and 41 other author(s). DSD, page 286-294. IEEE, (2021)The Next Generation of Exascale-Class Systems: The ExaNeSt Project.R. Ammendola, A. Biagioni, P. Cretaro, O. Frezza, F. Cicero, A. Lonardo, M. Martinelli, P. Paolucci, E. Pastorelli, F. Simula and 8 other author(s). DSD, page 510-515. IEEE Computer Society, (2017)GPU Peer-to-Peer Techniques Applied to a Cluster Interconnect.R. Ammendola, M. Bernaschi, A. Biagioni, M. Bisson, M. Fatica, O. Frezza, F. Cicero, A. Lonardo, E. Mastrostefano, P. Paolucci and 4 other author(s). IPDPS Workshops, page 806-815. IEEE, (2013)Virtual-to-Physical address translation for an FPGA-based interconnect with host and GPU remote DMA capabilities.R. Ammendola, A. Biagioni, O. Frezza, F. Cicero, A. Lonardo, P. Paolucci, D. Rossetti, F. Simula, L. Tosoratto, and P. Vicini. FPT, page 58-65. IEEE, (2013)NaNet: a flexible and configurable low-latency NIC for real-time trigger systems based on GPUs.R. Ammendola, A. Biagioni, O. Frezza, G. Lamanna, A. Lonardo, F. Cicero, P. Paolucci, F. Pantaleo, D. Rossetti, F. Simula and 3 other author(s). CoRR, (2013)LO-FA-MO: Fault Detection and Systemic Awareness for the QUonG Computing System.R. Ammendola, A. Biagioni, O. Frezza, F. Cicero, A. Lonardo, P. Paolucci, D. Rossetti, F. Simula, L. Tosoratto, and P. Vicini. SRDS, page 265-270. IEEE Computer Society, (2014)

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Disambiguation of "Frezza, Ottorino"

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Virtual-to-Physical address translation for an FPGA-based interconnect with host and GPU remote DMA capabilities.

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Ottorino Mazzetta

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Disambiguation of "Frezza, Ottorino"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Virtual-to-Physical address translation for an FPGA-based interconnect with host and GPU remote DMA capabilities.

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Ottorino Mazzetta

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Virtual-to-Physical address translation for an FPGA-based interconnect with host and GPU remote DMA capabilities.