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Disambiguation of "Krishnamurthy, Ram"

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A 230mV-950mV 2.8Tbps/W Unified SHA256/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS.

, , , , , , , and . ESSCIRC, page 98-101. IEEE, (2018)

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Mahalakshmi Krishnamurthy

Adarsh Krishnamurthy

Arvind Krishnamurthy

Johann Ram

Ram Gopal

 

Other publications of authors with the same name

Designing leakage tolerant, low power wide-OR dominos for sub-130nm CMOS technologies., , and . Microelectron. J., 36 (9): 801-809 (2005)Low voltage sensing techniques and secondary design issues for sub-90nm caches., , , , , and . ESSCIRC, page 413-416. IEEE, (2003)3GHz, 74mW 2-level Karatsuba 64b Galois field multiplier for public-key encryption acceleration in 45nm CMOS., , , , , , , , and . ESSCIRC, page 198-201. IEEE, (2010)A low-power 16-bit multiplier-accumulator using series-regulated mixed swing techniques., , and . CICC, page 499-502. IEEE, (1998)A burn-in tolerant dynamic circuit technique., , , , and . CICC, page 81-84. IEEE, (2002)A 9GHz 65nm Intel Pentium 4 Processor Integer Execution Core., , , , , , , , and . ISSCC, page 353-365. IEEE, (2006)A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores., , , , and . VLSI Design, page 273-278. IEEE Computer Society, (2008)A 54% Power-Saving Static Fully-Interruptible Single-Phase-Clocked Shared-Keeper Flip-Flop in 14nm CMOS., , , , , , , , , and . A-SSCC, page 137-140. IEEE, (2019)A 280mV 3.1pJ/code Huffman Decoder for DEFLATE Decompression Featuring Opportunistic Code Skip and 3-way Symbol Generation in 14nm Tri-gate CMOS., , , , , , , , , and . A-SSCC, page 263-266. IEEE, (2018)A Low-swing Signaling Circuit Technique for 65nm On-chip Interconnects., , , , and . SoCC, page 289-292. IEEE, (2006)