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Disambiguation of "Kaul, Himanshu"

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34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms.

, , , , , , , , , and . ESSCIRC, page 90-93. IEEE, (2018)

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Himanshu Raj

Himanshu Verma

Himanshu Tyagi

Himanshu Ghildiyal

Himanshu Patel

 

Other publications of authors with the same name

A 4900- $\mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 55 (4): 945-955 (2020)Investigating biocomplexity through the agent-based paradigm., and . Briefings Bioinform., 16 (1): 137-152 (2015)Future Performance Challenges in Nanometer Design., and . DAC, page 3-8. ACM, (2001)16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS., , , , , , , , , and . ISSCC, page 276-277. IEEE, (2014)A robust alternate repeater technique for high performance busses in the multi-core era., , , , and . ISCAS, page 372-375. IEEE, (2008)A 225-950mV 1.5Tbps/W Whirlpool Hashing Accelerator for Secure Automotive Platforms in 14nm CMOS., , , , , , , , and . CICC, page 1-4. IEEE, (2019)A robust edge encoding technique for energy-efficient multi-cycle interconnect., , , , and . ISLPED, page 68-73. ACM, (2007)μRNG: A 300-950mV 323Gbps/W all-digital full-entropy true random number generator in 14nm FinFET CMOS., , , , , , , , , and 1 other author(s). ESSCIRC, page 116-119. IEEE, (2015)A 230mV-950mV 2.8Tbps/W Unified SHA256/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS., , , , , , , and . ESSCIRC, page 98-101. IEEE, (2018)Optimized Fused Floating-Point Many-Term Dot-Product Hardware for Machine Learning Accelerators., , , , and . ARITH, page 84-87. IEEE, (2019)