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Disambiguation of "Krishnamurthy, Ram"

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Optimized Fused Floating-Point Many-Term Dot-Product Hardware for Machine Learning Accelerators.

, , , , and . ARITH, page 84-87. IEEE, (2019)

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Mahalakshmi Krishnamurthy

Adarsh Krishnamurthy

Arvind Krishnamurthy

Ram Gopal

Johann Ram

 

Other publications of authors with the same name

A 2.9Tb/s 8W 64-core circuit-switched network-on-chip in 45nm CMOS., , , , and . ESSCIRC, page 182-185. IEEE, (2008)2.4GHz, Double-Buffered, 4kb Standard-Cell-Based Register File with Low-Power Mixed-Frequency Clocking for Machine Learning Accelerators., , , , , , , , and . VLSI Technology and Circuits, page 22-23. IEEE, (2022)An 8.8GHz 198mW 16x64b 1R/1W variationtolerant register file in 65nm CMOS., , , , , and . ISSCC, page 1785-1797. IEEE, (2006)Ultra-low energy security circuits for IoT applications., , , and . ICCD, page 682-685. IEEE Computer Society, (2016)25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS., , , , , , , , , and 4 other author(s). ISSCC, page 392-394. IEEE, (2020)A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS., , , , , , , and . ISSCC, page 182-184. IEEE, (2012)A 1.9Gb/s 358mW 16-to-256 State Reconfigurable Viterbi Accelerator in 90nm CMOS., , , , and . ISSCC, page 256-600. IEEE, (2007)Split-Path Fused Floating Point Multiply Accumulate (FPMAC)., , , , , , , and . IEEE Symposium on Computer Arithmetic, page 17-24. IEEE Computer Society, (2013)A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking., , , , , , , , , and . VLSI Circuits, page 32-. IEEE, (2019)A 4900×m2 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition., , , , , , , , , and 2 other author(s). VLSI Circuits, page 234-. IEEE, (2019)