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Disambiguation of "Soenen, Eric"

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A 2.5 V 10 bit SAR ADC.

, , , , , and . VLSI Design, page 525-526. IEEE Computer Society, (1997)

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Johan Soenen

Friederike Erichsen-Wendt

Claus Erichsen

Kay Erichsen

Curt Erich

 

Other publications of authors with the same name

Energy Efficient Design Through Design and Technology Co-Optimization Near the Finish Line of CMOS Scaling., , , , and . A-SSCC, page 1-3. IEEE, (2021)Challenges at 45nm and beyond., , , , and . ICCAD, page 7. IEEE Computer Society, (2008)A 65nm, 1.15-0.15V, 99.99% Current-efficient Digital Low Dropout Regulator with Asynchronous Non-linear Control for Droop Mitigation., , , , , , , , , and 3 other author(s). ISCAS, page 1-5. IEEE, (2018)Physical design methodology for analog circuitsin a system-on-a-chip environment.. ISPD, page 73-74. ACM, (2009)Technology tradeoffs in the design of high performance analog to digital converters.. ICECS, page 7-11. IEEE, (2001)A 2.5 V 10 bit SAR ADC., , , , , and . VLSI Design, page 525-526. IEEE Computer Society, (1997)A robust digital DC-DC converter with rail-to-rail output range in 40nm CMOS., , , , , and . ISSCC, page 198-199. IEEE, (2010)A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs., , , , , , , and . IEEE J. Solid State Circuits, 53 (11): 3280-3292 (2018)A 72.6 dB SNDR 14b 100 MSPS Ring Amplifier Based Pipelined SAR ADC with Dynamic Deadzone Control in 16 nm CMOS., and . CICC, page 1-4. IEEE, (2020)A digital low drop-out regulator with wide operating range in a 16nm FinFET CMOS process., , and . A-SSCC, page 1-4. IEEE, (2015)