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CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing.

H. Furukawa, X. Wen, K. Miyase, Y. Yamato, S. Kajihara, P. Girard, L. Wang, and M. Tehranipoor. ATS, page 397-402. IEEE Computer Society, (2008)

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Kohei Tatsumi

Susanne Koheil

Mohamed Koheil

Other publications of authors with the same name

Adaptive ECC Techniques for Reliability and Yield Enhancement of Phase Change Memory.S. Lu, H. Li, and K. Miyase. IOLTS, page 226-227. IEEE, (2018)A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits.K. Miyase, M. Aso, R. Ootsuka, X. Wen, H. Furukawa, Y. Yamato, K. Enokimoto, and S. Kajihara. VTS, page 197-202. IEEE Computer Society, (2012)On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression.K. Enokimoto, X. Wen, K. Miyase, J. Huang, S. Kajihara, and L. Wang. VLSI Design, page 279-284. IEEE Computer Society, (2013)On Improving Defect Coverage of Stuck-at Fault Tests.K. Miyase, K. Terashima, S. Kajihara, X. Wen, and S. Reddy. Asian Test Symposium, page 216-223. IEEE Computer Society, (2005)A Method of Static Test Compaction Based on Don't Care Identification.K. Miyase, S. Kajihara, and S. Reddy. DELTA, page 392-395. IEEE Computer Society, (2002)Scan-Out Power Reduction for Logic BIST.S. Wang, Y. Sato, S. Kajihara, and K. Miyase. IEICE Trans. Inf. Syst., 96-D (9): 2012-2020 (2013)High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme.K. Miyase, X. Wen, H. Furukawa, Y. Yamato, S. Kajihara, P. Girard, L. Wang, and M. Tehranipoor. IEICE Trans. Inf. Syst., 93-D (1): 2-9 (2010)A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing.Y. Yamato, X. Wen, K. Miyase, H. Furukawa, and S. Kajihara. IEICE Trans. Inf. Syst., 94-D (4): 833-840 (2011)A Practical Online Error Detection Method for Functional Safety Using Three-Site Implications.K. Loki, Y. Kai, K. Miyase, and S. Kajihara. ITC, page 63-72. IEEE, (2022)On Test Data Volume Reduction for Multiple Scan Chain Designs.S. Reddy, K. Miyase, S. Kajihara, and I. Pomeranz. VTS, page 103-110. IEEE Computer Society, (2002)

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Disambiguation of "Miyase, Kohei"

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CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing.

Please choose a person to relate this publication to

Kohei Tatsumi

Kohei Tatsumi

Susanne Koheil

Mohamed Koheil

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Miyase, Kohei"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing.

Please choose a person to relate this publication to

Kohei Tatsumi

Kohei Tatsumi

Susanne Koheil

Mohamed Koheil

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing.