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Disambiguation of "Anders, Mark A."

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A 220-900mV 179Mcode/s 36pJ/code Canonical Huffman Encoder for DEFLATE Compression in 14nm CMOS.

, , , , , , , , , , , and . CICC, page 1-4. IEEE, (2019)

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Mark A Nusselein

Mark A Awabdy

Mark A Nusselein

Mark Yampolsky

Maßnahmen zur Sicherung von E2E-QoS bei verketteten Diensten. Uni München, (2009)

Mark Schütte

Crf2 - ein neues Antigen von Aspergillus fumigatus. TU Braunschweig, (2009)
 

Other publications of authors with the same name

A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 41 (1): 256-264 (2006)A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 52 (4): 940-949 (2017)A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 50 (1): 59-67 (2015)16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS., , , , , , , , , and . ISSCC, page 278-279. IEEE, (2014)An 8.8GHz 198mW 16x64b 1R/1W variationtolerant register file in 65nm CMOS., , , , , and . ISSCC, page 1785-1797. IEEE, (2006)A 2.9Tb/s 8W 64-core circuit-switched network-on-chip in 45nm CMOS., , , , and . ESSCIRC, page 182-185. IEEE, (2008)A 7Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS., , , , , , , and . VLSI Technology and Circuits, page 138-139. IEEE, (2022)2.4GHz, Double-Buffered, 4kb Standard-Cell-Based Register File with Low-Power Mixed-Frequency Clocking for Machine Learning Accelerators., , , , , , , , and . VLSI Technology and Circuits, page 22-23. IEEE, (2022)A 4900×m2 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition., , , , , , , , , and 2 other author(s). VLSI Circuits, page 234-. IEEE, (2019)A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking., , , , , , , , , and . VLSI Circuits, page 32-. IEEE, (2019)