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Design methodology for determining the number of stages in a cascaded time amplifier to minimize area consumption., , и . IEICE Electron. Express, 10 (11): 20130289 (2013)A low-offset cascaded time amplifier with reconfigurable inter-stage connection., , , и . IEICE Electron. Express, 11 (10): 20140203 (2014)An on-chip timing jitter measurement circuit using a self-referenced clock and a cascaded time difference amplifier with duty-cycle compensation., , , , и . A-SSCC, стр. 201-204. IEEE, (2011)Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges., , , , , , , и . ASP-DAC, стр. 103-104. IEEE, (2013)A clock jitter reduction circuit using gated phase blending between self-delayed clock edges., , , , , , , и . VLSIC, стр. 142-143. IEEE, (2012)Analysis of jitter accumulation in interleaved phase frequency detectors for high-accuracy on-chip jitter measurements., , , , , , и . ISOCC, стр. 146-149. IEEE, (2011)A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS., , , , , и . ASP-DAC, стр. 553-554. IEEE, (2012)