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High-Bandwidth Memory Interface, , и . Springer Briefs in Electrical and Computer Engineering Springer, (2014)Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip., , , и . IEEE Trans. Very Large Scale Integr. Syst., 21 (1): 173-177 (2013)Segmented Match-Line and Charge-Sharing Based Low-Cost TCAM., , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 69 (12): 5104-5108 (2022)A 0.88-pJ/bit 28Gb/s quad-rate 1-FIR 2-IIR decision feedback equalizer with 21dB loss compensation in 65nm CMOS process., и . IEICE Electron. Express, 18 (18): 20210253 (2021)A 1.62-5.4-Gb/s Receiver for DisplayPort Version 1.2a With Adaptive Equalization and Referenceless Frequency Acquisition Techniques., , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (10): 2691-2702 (2017)A 20Gb/s/pin Single-ended Transmitter with FEXT Compensation Technique., , , , и . ICEIC, стр. 1-3. IEEE, (2021)A 28Gb/s quad-rate 1-FIR 2-IIR DFE with 20dB Loss Compensation in 65nm CMOS Process., , , , и . ICEIC, стр. 1-4. IEEE, (2021)29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces., , , , , , и . ISSCC, стр. 490-491. IEEE, (2017)Small-area high-accuracy ODT/OCD by calibration of global on-chip for 512M GDDR5 application., , , , , и . CICC, стр. 717-720. IEEE, (2009)A 32 Gb/s Rx only equalization transceiver with 1-tap speculative FIR and 2-tap direct IIR DFE., , , и . VLSI Circuits, стр. 1-2. IEEE, (2016)