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An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI Devices.

, , , , , , , , , , , , , and . ISSCC, page 1-3. IEEE, (2022)

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Circuit design for beyond von Neumann applications using emerging memory: From nonvolatile logics to neuromorphic computing., , , , , , , , , and . ISQED, page 23-28. IEEE, (2017)A 28nm Nonvolatile AI Edge Processor using 4Mb Analog-Based Near-Memory-Compute ReRAM with 27.2 TOPS/W for Tiny AI Edge Devices., , , , , , , , , and 8 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)34.2 A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices., , , , , , , , , and 5 other author(s). ISSCC, page 568-570. IEEE, (2024)29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification., , , , , and . ISSCC, page 404-406. IEEE, (2021)An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI Devices., , , , , , , , , and 4 other author(s). ISSCC, page 1-3. IEEE, (2022)A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS., , , , , , , , and . IEEE J. Solid State Circuits, 56 (1): 188-198 (2021)A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 59 (1): 52-64 (January 2024)A 2.38 MCells/mm2 9.81 -350 TOPS/W RRAM Compute-in-Memory Macro in 40nm CMOS with Hybrid Offset/IOFF Cancellation and ICELL RBLSL Drop Mitigation., , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors., , , , , , , , , and 1 other author(s). ISSCC, page 496-498. IEEE, (2018)A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking., , , , , , , , , and 1 other author(s). ISSCC, page 426-427. IEEE, (2023)