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Disambiguation of "Huang, Chao-Tsung"

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System analysis of VLSI architecture for motion-compensated temporal filtering.

, , , , and . ICIP (3), page 992-995. IEEE, (2005)

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Tsung-Yü Chao

Huang-Tsung Kuo

Chao-Huang Wei

Chao-Hua Huang

Tsing-Tshih Tsung

 

Other publications of authors with the same name

23.2 A 1920×1080 30fps 611 mW five-view depth-estimation processor for light-field applications., , , , , and . ISSCC, page 1-3. IEEE, (2015)Generic RAM-based architecture for two-dimensional discrete wavelet transform with line-based method., , and . APCCAS (1), page 363-366. IEEE, (2002)VLSI Architecture for Lifting-Based Shape-Adaptive Discrete Wavelet Transform with Odd-Symmetric Filters., , and . VLSI Signal Processing, 40 (2): 175-188 (2005)A 95pJ/label Wide-Range Depth-Estimation Processor for Full-HD Light-Field Applications on FPGA., , , , , and . A-SSCC, page 261-262. IEEE, (2018)FIR Filter Design and Implementation for Phase-Based Processing., , and . ICASSP, page 1748-1752. IEEE, (2020)A HD 31fps 7×7-View Light-Field Factorization Processor for Dual-Layer 3D Factored Display., , , , , and . ISSCC, page 1-3. IEEE, (2022)Sub-pixel disparity estimation in continuous space., , , and . ICCE-TW, page 114-115. IEEE, (2015)On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform., , , , and . IEEE Trans. Circuits Syst. Video Techn., 17 (7): 814-822 (2007)Ernet Family: Hardware-Oriented Cnn Models For Computational Imaging Using Block-Based Inference.. ICASSP, page 1643-1647. IEEE, (2020)System Analysis of VLSI Architecture for 5/3 and 1/3 Motion-Compensated Temporal Filtering., , , , and . IEEE Trans. Signal Process., 54 (10): 4004-4014 (2006)