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11.4 IBM NorthPole: An Architecture for Neural Network Inference with a 12nm Chip.

A. Cassidy, J. Arthur, F. Akopyan, A. Andreopoulos, R. Appuswamy, P. Datta, M. DeBole, S. Esser, C. Otero, J. Sawada, B. Taba, A. Amir, D. Bablani, P. Carlson, M. Flickner, R. Gandhasri, G. Garreau, M. Ito, J. Klamo, J. Kusnitz, N. McClatchey, J. McKinstry, Y. Nakamura, T. Nayak, W. Risk, K. Schleupen, B. Shaw, J. Sivagnaname, D. Smith, I. Terrizzano, T. Ueda, and D. Modha. ISSCC, page 214-215. IEEE, (2024)

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Carlos Ortega Grau

Lourdes Otero León

Concepción Otero Moreno

Alfonso Ortega

Alcides Ortega

Other publications of authors with the same name

Traducing Software Voice-Pattern-Detection Applications into Hardware Systems.C. Nieto-Granda, S. Díaz-Pier, C. Ortega-Otero, and R. Oropeza. CONIELECOMP, page 195-200. IEEE Computer Society, (2005)11.4 IBM NorthPole: An Architecture for Neural Network Inference with a 12nm Chip.A. Cassidy, J. Arthur, F. Akopyan, A. Andreopoulos, R. Appuswamy, P. Datta, M. DeBole, S. Esser, C. Otero, J. Sawada and 22 other author(s). ISSCC, page 214-215. IEEE, (2024)IBM NorthPole Neural Inference Machine.D. Modha, F. Akopyan, A. Andreopoulos, R. Appuswamy, J. Arthur, A. Cassidy, P. Datta, M. DeBole, S. Esser, C. Otero and 22 other author(s). HCS, page 1-58. IEEE, (2023)Variability in 3-D integrated circuits.F. Akopyan, C. Otero, D. Fang, S. Jackson, and R. Manohar. CICC, page 659-662. IEEE, (2008)ULSNAP: An ultra-low power event-driven microcontroller for sensor network nodes.C. Otero, J. Tse, R. Karmazin, B. Hill, and R. Manohar. ISQED, page 667-674. IEEE, (2014)A split-foundry asynchronous FPGA.B. Hill, R. Karmazin, C. Otero, J. Tse, and R. Manohar. CICC, page 1-4. IEEE, (2013)Static Power Reduction Techniques for Asynchronous Circuits.C. Otero, J. Tse, and R. Manohar. ASYNC, page 52-61. IEEE Computer Society, (2010)Timing Driven Placement for Quasi Delay-Insensitive Circuits.R. Karmazin, S. Jr., C. Otero, and R. Manohar. ASYNC, page 45-52. IEEE Computer Society, (2015)AES Hardware-Software Co-design in WSN.C. Otero, J. Tse, and R. Manohar. ASYNC, page 85-92. IEEE Computer Society, (2015)Automatic obfuscated cell layout for trusted split-foundry design.C. Otero, J. Tse, R. Karmazin, B. Hill, and R. Manohar. HOST, page 56-61. IEEE Computer Society, (2015)

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Disambiguation of "Otero, Carlos Ortega"

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11.4 IBM NorthPole: An Architecture for Neural Network Inference with a 12nm Chip.

Please choose a person to relate this publication to

Carlos Ortega Grau

Lourdes Otero León

Concepción Otero Moreno

Alfonso Ortega

Alcides Ortega

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Otero, Carlos Ortega"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 11.4 IBM NorthPole: An Architecture for Neural Network Inference with a 12nm Chip.

Please choose a person to relate this publication to

Carlos Ortega Grau

Lourdes Otero León

Concepción Otero Moreno

Alfonso Ortega

Alcides Ortega

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
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URL
DOI
BibTeX
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APA
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11.4 IBM NorthPole: An Architecture for Neural Network Inference with a 12nm Chip.