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Disambiguation of "Kameyama, Michitaka"

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A Bit-Serial Reconfigurable VLSI Based on a Multiple-Valued X-Net Data Transfer Scheme.

, and . IEICE Trans. Inf. Syst., 96-D (7): 1449-1456 (2013)

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Michitaka Ota

Shin'ichi Kameyama

 

Other publications of authors with the same name

A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment., and . APCCAS, page 1803-1806. IEEE, (2006)Design of a Collision Detection VLSI Processor Based on Minimization of Area-Time Products., and . ICRA, page 3691-3696. IEEE Computer Society, (1998)Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit., , , and . ISCAS, page 3017-3020. IEEE, (2012)An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture., , , and . ASP-DAC, page 89-90. IEEE, (2011)Low-power multiple-valued current-mode integrated circuit with current-source control and its application., , and . ASP-DAC, page 413-418. IEEE, (1997)One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic Image Processing., , and . ISMVL, page 175-182. IEEE Computer Society, (1997)Quaternary Universal-Literal CAM for Cellular Logic Image Processing., , and . ISMVL, page 224-229. IEEE Computer Society, (1996)Novel Switch Block Architecture Using Non-Volatile Functional Pass-Gate for Multi-Context FPGAs., , , and . ISVLSI, page 46-50. IEEE Computer Society, (2005)Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors., , and . ISVLSI, page 193-198. IEEE Computer Society, (2006)Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 98-A (12): 2658-2669 (2015)