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Disambiguation of "Niemier, Michael T."

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Reliable and high performance STT-MRAM architectures based on controllable-polarity devices.

, , , , , and . ICCD, page 343-350. IEEE Computer Society, (2015)

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Kay Niemier

Michael R T Macnair

T Peters

T Frieberg

T Masselink

 

Other publications of authors with the same name

In-Memory Nearest Neighbor Search with FeFET Multi-Bit Content-Addressable Memories., , , , , , , , and . CoRR, (2020)Petaflop Computing for Protein Folding., , , , and . PPSC, (2001)A Flash-Based Multi-Bit Content-Addressable Memory with Euclidean Squared Distance., , , , , and . ISLPED, page 1-6. IEEE, (2021)MIMHD: Accurate and Efficient Hyperdimensional Inference Using Multi-Bit In-Memory Computing., , , , , and . ISLPED, page 1-6. IEEE, (2021)GC-eDRAM design using hybrid FinFET/NC-FinFET., , , , and . ISLPED, page 199-204. ACM, (2020)Modeling and Benchmarking Computing-in-Memory for Design Space Exploration., , , , , , , and . ACM Great Lakes Symposium on VLSI, page 39-44. ACM, (2020)Attention-in-Memory for Few-Shot Learning with Configurable Ferroelectric FET Arrays., , , and . ASP-DAC, page 49-54. ACM, (2021)Eva-CAM: A Circuit/Architecture-Level Evaluation Tool for General Content Addressable Memories., , , , , , , and . DATE, page 1173-1176. IEEE, (2022)SearcHD: A Memory-Centric Hyperdimensional Computing With Stochastic Training., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (10): 2422-2433 (2020)Tunnel FET Current Mode Logic for DPA-Resilient Circuit Designs., , , , , and . IEEE Trans. Emerg. Top. Comput., 5 (3): 340-352 (2017)