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Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture.

Q. Zhao, Y. Liu, W. Sun, J. Zhao, H. Yao, X. Guo, and H. Yang. DAC, page 80:1-80:6. ACM, (2017)

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Wenyu Huo

Wenyu Dong

Yü-Sün Sun

Deming Sun

Hongtao Sun

Other publications of authors with the same name

A self-adaptive projection method with improved step-size for solving variational inequalities.X. Yan, D. Han, and W. Sun. Comput. Math. Appl., 55 (4): 819-832 (2008)Mechanical strain and temperature aware design methodology for thin-film transistor based pseudo-CMOS logic array.W. Sun, Y. Huang, Q. Zhao, F. Qiao, T. Ho, X. Guo, H. Yang, and Y. Liu. ASP-DAC, page 645-650. IEEE, (2018)Sparsity-Aware Non-Volatile Computing-In-Memory Macro with Analog Switch Array and Low-Resolution Current-Mode ADC.Y. Huang, Y. He, J. Yue, W. Sun, H. Yang, and Y. Liu. ASP-DAC, page 684-689. IEEE, (2022)On duality theory for non-convex semidefinite programming.W. Sun, C. Li, and R. de Sampaio. Ann. Oper. Res., 186 (1): 331-343 (2011)A hybrid splitting method for variational inequality problems with separable structure.H. He, D. Han, W. Sun, and Y. Chen. Optim. Methods Softw., 28 (4): 725-742 (2013)An iteratively approximated gradient projection algorithm for sparse signal reconstruction.Z. Liu, Z. Wei, and W. Sun. Appl. Math. Comput., (2014)A full-NT-step infeasible interior-point algorithm for SDP based on kernel functions.Z. Liu, and W. Sun. Appl. Math. Comput., 217 (10): 4990-4999 (2011)A 4-Mbps 41-pJ/bit On-off Keying Transceiver for Body-channel Communication with Enhanced Auto Loss Compensation Technique.J. Zhao, J. Mao, W. Sun, Y. Huang, Y. Yang, H. Yang, and Y. Liu. A-SSCC, page 173-176. IEEE, (2019)A derivative-free algorithm for spherically constrained optimization.M. Xi, W. Sun, Y. Chen, and H. Sun. J. Glob. Optim., 76 (4): 841-861 (2020)A 28-nm Floating-Point Computing-in-Memory Processor Using Intensive-CIM Sparse-Digital Architecture.S. Yan, J. Yue, C. He, Z. Wang, Z. Cong, Y. He, M. Zhou, W. Sun, X. Li, C. Dou and 4 other author(s). IEEE J. Solid State Circuits, 59 (8): 2630-2643 (August 2024)

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Disambiguation of "Sun, Wenyu"

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Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture.

Please choose a person to relate this publication to

Wenyu Huo

Wenyu Dong

Yü-Sün Sun

Deming Sun

Hongtao Sun

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Sun, Wenyu"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture.

Please choose a person to relate this publication to

Wenyu Huo

Wenyu Dong

Yü-Sün Sun

Deming Sun

Hongtao Sun

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture.