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Global transaction ordering in Network-on-Chips for post-silicon validation., и . ISQED, стр. 284-289. IEEE, (2011)Tutorial: "Post silicon debug of SOC designs"., и . SoCC, стр. 18. IEEE, (2011)A small biped entertainment robot exploring attractive applications., , , , и . ICRA, стр. 471-476. IEEE, (2003)Object-oriented analysis and design of hardware/software co-designs with dependence analysis for design reuse., , и . IRI, стр. 318-325. IEEE Systems, Man, and Cybernetics Society, (2005)RTL datapath optimization using system-level transformations., , , и . ISQED, стр. 309-316. IEEE, (2014)Specification and formal verification of power gating in processors., и . ISQED, стр. 604-610. IEEE, (2014)On variable ordering of binary decision diagrams for the application of multi-level logic synthesis., , и . EURO-DAC, стр. 50-54. EEE Computer Society, (1991)Automatic High-Level Data-Flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition., , , и . IEEE Trans. Computers, 64 (6): 1579-1593 (2015)234 scheduling of 3-2 and 2-1 eliminations for parallel image compositing using non-power-of-two number of processes., , и . HPCS, стр. 421-428. IEEE, (2015)Early case splitting and false path detection to improve high level ATPG techniques., и . ISCAS, стр. 1463-1466. IEEE, (2011)