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In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC.

E. Nurvitadhi, J. Cook, A. Mishra, D. Marr, K. Nealis, P. Colangelo, A. Ling, D. Capalija, U. Aydonat, A. Dasu, and S. Shumarayev. FPL, page 106-110. IEEE Computer Society, (2018)

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Stephen Cook

Ralph Cook

Andrew Cook

Neil Cook

Nicholas Cook

Other publications of authors with the same name

Mapping computation kernels to clustered programmable-reconfigurable processors.J. Cook, L. Baugh, D. Gottlieb, and N. Carter. FPT, page 435-438. IEEE, (2003)WRPN: Wide Reduced-Precision Networks.A. Mishra, E. Nurvitadhi, J. Cook, and D. Marr. ICLR (Poster), OpenReview.net, (2018)In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only).E. Nurvitadhi, J. Cook, A. Mishra, D. Marr, K. Nealis, P. Colangelo, A. Ling, D. Capalija, U. Aydonat, S. Shumarayev and 1 other author(s). FPGA, page 287. ACM, (2018)WRPN: Training and Inference using Wide Reduced-Precision Networks.A. Mishra, J. Cook, E. Nurvitadhi, and D. Marr. CoRR, (2017)WRPN: Wide Reduced-Precision Networks.A. Mishra, E. Nurvitadhi, J. Cook, and D. Marr. CoRR, (2017)In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC.E. Nurvitadhi, J. Cook, A. Mishra, D. Marr, K. Nealis, P. Colangelo, A. Ling, D. Capalija, U. Aydonat, A. Dasu and 1 other author(s). FPL, page 106-110. IEEE Computer Society, (2018)Exploiting Pipelining to Tolerate Wire Delays in a Programmable-Reconfigurable Processor.C. Wang, N. Carter, R. Kujoth, J. Cook, and D. Gottlieb. FPL, page 57-64. IEEE, (2005)Characterizing and optimizing the memory footprint of de novo short read DNA sequence assembly.J. Cook, and C. Zilles. ISPASS, page 143-152. IEEE Computer Society, (2009)Blueshift: Designing processors for timing speculation from the ground up.B. Greskamp, L. Wan, U. Karpuzcu, J. Cook, J. Torrellas, D. Chen, and C. Zilles. HPCA, page 213-224. IEEE Computer Society, (2009)Clustered programmable-reconfigurable processors.D. Gottlieb, J. Cook, J. Walstrom, S. Ferrera, C. Wang, and N. Carter. FPT, page 134-141. IEEE, (2002)

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Disambiguation of "Cook, Jeffrey J."

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In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC.

Please choose a person to relate this publication to

Stephen Cook

Ralph Cook

Andrew Cook

Neil Cook

Nicholas Cook

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Cook, Jeffrey J."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC.

Please choose a person to relate this publication to

Stephen Cook

Ralph Cook

Andrew Cook

Neil Cook

Nicholas Cook

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC.